International Journal of Scientific and Research Publications

IJSRP, Volume 5, Issue 6, June 2015 Edition [ISSN 2250-3153]


Design and Development of Verification Environment to Verify GPIO Core using UVM
      Basavaraj Police Patil D, Anuradha J P, Mrs.Shanthi V A
Abstract: The GPIO core design provides a general purpose input/output interface to a 32-bit On-Chip Peripheral Bus (OPB). This GPIO core requires simple output and/or input software controlled signals and implements the functions that are not implemented using dedicated controllers in the system. Almost all FPGA boards contain GPIO peripheral. In this project we are atomizing the functions of the GPIO core by writing the code in VERILOG and simulating it in QUESTASIM. In this project we verify the all functions of GPIO core by writing verification code in UVM with different test cases. The functional and code coverage and functional verification of the GPIO RTL design is carried out for the better optimum design.

Reference this Research Paper (copy & paste below code):

Basavaraj Police Patil D, Anuradha J P, Mrs.Shanthi V A (2018); Design and Development of Verification Environment to Verify GPIO Core using UVM; Int J Sci Res Publ 5(6) (ISSN: 2250-3153). http://www.ijsrp.org/research-paper-0615.php?rp=P424241
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