IJSRP, Volume 4, Issue 1, January 2014 Edition [ISSN 2250-3153]
G. Divya, B. Subbarami Reddy, P. Bhagyalakshmi
This paper presents power analysis of the full adder cells reported as having a low PDP (Power Delay Product), by means of speed, power consumption and area. These full adders were designed upon various logic styles to derive the sum and carry outputs. Two new high-speed and low-power full adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced PDP (Power-delay product). These all full adder cells designed using a TDK 90 nm CMOS technology.