International Journal of Scientific and Research Publications

IJSRP, Volume 3, Issue 11, November 2013 Edition [ISSN 2250-3153]


Error Tolerant Adder
      Chetan Deo Singh, Yuvraj Singh
Abstract: The addition of two binary numbers is the most fundamental and widely used arithmetic operation. This operation is used in microprocessors, digital signal processors, data processing application specific integrated circuits and many more. There are many adders designed till now. ETA is one such efficient adder which speeds up binary addition. ETA is the Error Tolerant Adder which consumes less power and delay. Design of ETA is done using backend tool under real time simulation conditions. This paper compares the performance of the ETA in terms of accuracy, delay and power consumption with that of conventional adders.

Reference this Research Paper (copy & paste below code):

Chetan Deo Singh, Yuvraj Singh (2018); Error Tolerant Adder; Int J Sci Res Publ 3(11) (ISSN: 2250-3153). http://www.ijsrp.org/research-paper-1113.php?rp=P231981
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