International Journal of Scientific and Research Publications

IJSRP, Volume 3, Issue 9, September 2013 Edition [ISSN 2250-3153]


A Novel Approach of Area Optimized and pipelined FPGA Implementation of AES Encryption and Decryption
      K.Sireesha, S.Madhava Rao
Abstract: In this paper we present an architecture to implement Advanced Encryption Standard (AES) Rijndael algorithm in reconfigurable hardware. Rijndael algorithm is the new AES adopted by the National Institute of Standards and Technology (NIST) to replace existing Data Encryption Standard (DES). Compared to software implementation, hardware implementation of Rijndael algorithm provides more physical security as well as higher speed. The first factor to be considered on implementing AES is the application. High-speed designs are not always desired solutions. In some applications, such as mobile computing and wireless communications, smaller throughput is demanded. Architecture presented uses memory modules (i.e., Dual-Port RAMs) of Field-Programmable Gate Array (FPGAs) for storing all the results of the fixed operations (i.e., Look-Up Table), and Digital Clock Manager (DCM) that we used effectively to optimize the execution time, reduce design area and facilitates implementation in FPGA. The architecture consumes only 326 slices plus 3 Block Random Access Memory (BRAMs). The throughput obtained was of 270 Mbits/s. The target hardware used in this paper is Spartan XC3S500E FPGA from Xilinx.

Reference this Research Paper (copy & paste below code):

K.Sireesha, S.Madhava Rao (2018); A Novel Approach of Area Optimized and pipelined FPGA Implementation of AES Encryption and Decryption; Int J Sci Res Publ 3(9) (ISSN: 2250-3153). http://www.ijsrp.org/research-paper-0913.php?rp=P211710
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