International Journal of Scientific and Research Publications

IJSRP, Volume 4, Issue 8, August 2014 Edition [ISSN 2250-3153]

Design of 32Bit Carry-lookahead Adder using Constant Delay Logic
      K.Santosh, Sri G.Ramesh
Abstract: This paper presents an enhanced 32-bit carry look-ahead(CLA) adder implementing using the constant delay (CD) logic, targeting at full-custom high-speed applications. The CD characteristic of this logic style regardless of the logic type makes it suitable in implementing complicated logic expressions such as addition. CD logic exhibits a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage is ready. This feature offers performance advantage over static and dynamic domino logic styles in a single-cycle multistage circuit block. Several design considerations including timing window width adjustment and clock distribution are discussed. Using 65-nm general-purpose CMOS technology, the proposed logic demonstrates an average speed up of 94% and 56% over static and dynamic domino logic, respectively, in five different logic gates. Simulation results of 8-bit ripple carry adders show that CD logic is 39% and 23% faster than the static and dynamic-based adders, respectively. CD logic also demonstrates 39% speedup and 64%(22%) energy-delay product (EDP) reduction from static logic at 100% (10%) data activity in 32-bit carry look ahead adders. For 8-bit Wallace tree multiplier, CD logic achieves a similar speedup with at least 50% EDP reduction across all data activities.

Reference this Research Paper (copy & paste below code):

K.Santosh, Sri G.Ramesh (2018); Design of 32Bit Carry-lookahead Adder using Constant Delay Logic; Int J Sci Res Publ 4(8) (ISSN: 2250-3153). http://www.ijsrp.org/research-paper-0814.php?rp=P323053
©️ Copyright 2011-2023 IJSRP - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.