Abstract: Crosstalk in VLSI interconnects is a major constraint in DSM and UDSM technology. Among various strategies followed for its minimization, shield insertion between aggressor and victim lines is one of the most prominent options. Placing shields around a victim signal line is a common way to enhance signal integrity while minimizing delay uncertainty. This paper analyzes the extent of crosstalk in capacitive coupled interconnects and minimizes the same through shield insertion. Also design guidelines for shielding in the presence of power/ground (P/G) noise are illustrated in this paper. The effects of P/G noise on crosstalk is analyzed for different line lengths, line widths, and interconnect driver resistances. Considering the P/G noise, a shield line can degrade the signal integrity due to increased P/G noise coupling on the victim line. A RC interconnect model is used to investigate the effects of coupling capacitance on the crosstalk noise. Physical spacing and shield insertion are compared in terms of the delay on the victim line for several technology parameters. Dual port SRAM cells contain a second set of access transistors designed to allow a second read from the cell. As device sizes shrink, the spacing between conductors is reduced to the point where crosstalk between second pair of access runners within the same cell area of a dual port device becomes a significant design issue. Techniques for reducing capacitive coupling between these access lines are considered here. Additionally, the effects of technology scaling on P/G noise and shielding efficiency between bit lines are discussed, and related design tradeoffs are addressed. Design tools used to build circuit schematic is Cadence Virtuoso Design Platform, HSpice Simulator for simulation of schematics and CosmosScope (CScope) for observing the waveforms.