IJSRP, Volume 3, Issue 8, August 2013 Edition [ISSN 2250-3153]
Laxman Shanigarapu, Bhavana P. Shrivastava
Adders are the basic building blocks of any processor or data path application. In adder design carry generation is the critical path. To reduce the power consumption of data path we need to reduce number of transistors of the adder. Carry Select Adder is one of the fast adder used in many data path applications. There is a chance to reduce the area, power and delay in the CSLA structure. The proposed design is implemented by using D-latch instead of using RCA cascade structure for Cin=0 or Cin=1. In this proposed design power and delay is reduced to 10.8% and 4.6% for 8bit, 17.73% and 49.3% for 16bit, 20% and 44.5% for 32bit, 21.9% and 59.8% for 64bit when compared to the Regular Carry Select Adder (CSLA). Power and delay is reduced to 4.43% and 37.23% for 8bit, 12.37% and 37.8% for 16bit, 14.06% and 45.68% for 32bit, 14.43% and 50.57% for 64bit when compared to the modified CSL adders (BEC). The delay is reduced 37.24% for 8bit, 60.4% for 16bit, 61.6% for 32bit, 14.43% and 56.74% for 64bit when compared to the modified CSL adder (WITHOUT USING MULTIPLEXER).