International Journal of Scientific and Research Publications

IJSRP, Volume 3, Issue 8, August 2013 Edition [ISSN 2250-3153]


Design Tradeoff Analysis and Implementation of Digital Binary Adders Using Verilog
      Priyanka Pawar, Dr. Vaibhav Neema
Abstract: Hardware designs targeting communication and DSP applications consists of a large number of data path elements such as adders, multipliers, comparators, shifter etc. These elements are main contributors to the power consumption of digital circuits. At present, most of the popular hardware synthesis tools give higher priority to delay. So the synthesis tools tend to generate data path architecture for faster implementation.

Reference this Research Paper (copy & paste below code):

Priyanka Pawar, Dr. Vaibhav Neema (2018); Design Tradeoff Analysis and Implementation of Digital Binary Adders Using Verilog; Int J Sci Res Publ 3(8) (ISSN: 2250-3153). http://www.ijsrp.org/research-paper-0813.php?rp=P201561
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