IJSRP, Volume 6, Issue 5, May 2016 Edition [ISSN 2250-3153]
Vandana Prajapati, Uday Panwar
In digital world multimedia and DSP based applications will work on some certain clock pulse and as we know, clock signal The clock signal consumes maximum applied power and this is a major drawback in digital synchronous circuit. Clock gating is an important technique of reducing the dynamic power losses in digital circuits. In a typical synchronous circuit such as the general purpose ALU multimedia, only a portion of the operating circuit is active at any given time and other circuit are remain inactive. Hence, by inactive the other circuit, the unnecessary power dissipation can be reduce. By using this approach dynamic power losses can be reduce.The new propose work implements another gated clock technique by using D flip flop and make comparative analysis between various clock gating technique.