International Journal of Scientific and Research Publications

IJSRP, Volume 4, Issue 5, May 2014 Edition [ISSN 2250-3153]


Power and Delay Optimized Edge Triggered Flip-Flop for low power microcontrollers
      Sameer Gull Alie, Ms.Tarana Afrin Chandel, Jehangir Rashid dar
Abstract: The demand for low power circuit design has increased tremendously due to explosive growth of battery operated portable devices like Microcontroller.Microcontroller uses register blocks that are inturn consists of flip flops. The mandate to reduce system power consumption and design energy-efficient ICs has led to the increasing use of low-power IC design techniques that prolong the battery life. In this paper, a novel highly efficient power and delay optimized True Single Phase clocked (TPSC) edge triggered flip-flop has been proposed. The proposed circuit uses lesser number of transistors than the conventional transmission gate D flip-flop that reduce the overall power and delay.The proposed design is also free from both glitch and charge sharing problems making it suitable for high speed and low power applications.

Reference this Research Paper (copy & paste below code):

Sameer Gull Alie, Ms.Tarana Afrin Chandel, Jehangir Rashid dar (2018); Power and Delay Optimized Edge Triggered Flip-Flop for low power microcontrollers; Int J Sci Res Publ 4(5) (ISSN: 2250-3153). http://www.ijsrp.org/research-paper-0514.php?rp=P292640
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