International Journal of Scientific and Research Publications

IJSRP, Volume 3, Issue 5, May 2013 Edition [ISSN 2250-3153]


Area and Power Efficient Router Design for Network on Chip
      Bhavana Prakash Shrivastava, Kavita Khare
Abstract: As network on chip (NoC) systems become more prevalent in today’s industry. Routers and interconnection networks are the main components of NoC. Therefore, there is a need to obtain low area and power models for these components so that we can better understand the area and power tradeoffs. In this paper a low- area and power efficient NoC architecture is proposed by eliminating the virtual channels. Buffers are replaced by elastic buffer. In order to get the advantage of both buffered and buffer less the cross bar is split in to two parts. Implementation is done in Micro wind 3.5 the proposed router area is reduced by 47.89% and power is reduced by 11.2% compared to base line router accordingly.

Reference this Research Paper (copy & paste below code):

Bhavana Prakash Shrivastava, Kavita Khare (2018); Area and Power Efficient Router Design for Network on Chip; Int J Sci Res Publ 3(5) (ISSN: 2250-3153). http://www.ijsrp.org/research-paper-0513.php?rp=P171169
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