Abstract: Weighted sets consist of three weights ,namely 0,1,and 0.5 have been successfully use so far for test pattern generation, since they gives both low testing time and low consumed power. Since accumulators are generally found in current VLSI chips, this scheme can be effectively made to use drive down the hardware of BIST pattern generation, as well. From the execution results, it is proved that the testing power for the proposed method is reduced by a considerable percentage. In accumulators used the adder, if we RCA adder or CLA adder its consume the more power and required more gates . If we kogges stone adder its required less power and less gates. Comparisons with previously presented schemes indicate that the recommended scheme compares favorably regarding required hardware.