Abstract: Large capacity content addressable memory (CAM) is a key element in wide variety of applications. A major challenge in realization of such systems is the complexities of scaling MOS transistors. Converges of different technologies, which are well-matched with CMOS processing may allow extension of Moore’s law for a new years. This paper provides a new approach towards the design and modeling of memristor based CAM (MCAM) using a combination of MOS devices to form a core of a memory or logic cell that forms the building block of the CAM architecture. The non volatile characteristics and the nanoscale geometry together with compatibility of the memristor increases the packing density with CMOS processing technology , provides for the new approaches towards power management through disabling CAM blocks without loss of stored data, reduces power indulgence, and has scope for speed improvement as the technology matures.