International Journal of Scientific and Research Publications

IJSRP, Volume 4, Issue 3, March 2014 Edition [ISSN 2250-3153]


Implementation of Efficient 16-Bit MAC Using Modified Booth Algorithm and Different Adders
      M.Karthikkumar, D.Manoranjitham, K.Praveenkumar
Abstract: The proposed system is an efficient implementation of 16-bit Multiplier- Accumulator using Radix-8 and Radix-16 Modified Booth Algorithm and seven different adders (SPST Adder, Parallel Prefix Adder, Carry Select Adder, Error Tolerant Adder, Hybrid Prefix Adder, Modified Area Efficient Carry Select Adder, Parallel Binary Adder) are using VHDL. This proposed system provides low power, high speed and less delay.

Reference this Research Paper (copy & paste below code):

M.Karthikkumar, D.Manoranjitham, K.Praveenkumar (2018); Implementation of Efficient 16-Bit MAC Using Modified Booth Algorithm and Different Adders; Int J Sci Res Publ 4(3) (ISSN: 2250-3153). http://www.ijsrp.org/research-paper-0314.php?rp=P272448
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