Abstract: In this manuscript, an unusual adaptive FIR filter using distributed arithmetic (DA) for area efficient design is implemented. DA is bit-serial computational action and uses parallel look-up table (LUTs) apprise and equivalent implementation of filtering and weight-update operations to appliance high throughput filter rates irrespective of the filter length. The full adder based conditional signed carry save accumulation for DA-based inner product computation is swapped and design by using 10 transistor full adder based carry save accumulation of shift accumulation, with the intention of the proposed design, it can reduce the area complexity and power consumption. The least-mean-square (LMS) algorithm adaptation is functioned to update the weight and abate the mean square error between the assessed and chosen output. The weight increment block based adder/subtractor cells is exchanged by carry save adder in order to reduce area difficulty. It comprises of multiplexors, smaller LUT, and practically half the number of adders contrasted to the present DA-based design.