Abstract: Even a small transition delays and little faults create major concern in digital circuits. It Produce greater impact on not only for simple memory but also for most of the memory applications. So, the majority logic decoders implemented with quasi cyclic LDPC codes are used to correct those problems in a digital circuit. In this technique majority logic decoder is used as fault detector due to usage of quasi cyclic LDPC codes the number of taps N can be reduced in the decoder to get minimum accessing time and lower area overhead.