International Journal of Scientific and Research Publications

IJSRP, Volume 3, Issue 3, March 2013 Edition [ISSN 2250-3153]


An Efficient Majority Logic Fault Detection to reduce the Accessing time for Memory Applications
      R.Meenaakshi Sundhari, C.Sundarrasu, M.Karthikkumar
Abstract: Even a small transition delays and little faults create major concern in digital circuits. It Produce greater impact on not only for simple memory but also for most of the memory applications. So, the majority logic decoders implemented with quasi cyclic LDPC codes are used to correct those problems in a digital circuit. In this technique majority logic decoder is used as fault detector due to usage of quasi cyclic LDPC codes the number of taps N can be reduced in the decoder to get minimum accessing time and lower area overhead.

Reference this Research Paper (copy & paste below code):

R.Meenaakshi Sundhari, C.Sundarrasu, M.Karthikkumar (2018); An Efficient Majority Logic Fault Detection to reduce the Accessing time for Memory Applications; Int J Sci Res Publ 3(3) (ISSN: 2250-3153). http://www.ijsrp.org/research-paper-0313.php?rp=P15850
©️ Copyright 2011-2022 IJSRP - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.