International Journal of Scientific and Research Publications

IJSRP, Volume 3, Issue 1, January 2013 Edition [ISSN 2250-3153]


Modeling and Architectural Simulations of the Statistical Static Timing Analysis of the Non-Gaussian Variation Sources for VLSI Circuits
      Abu M. Baker, Yingtao Jiang
Abstract: As CMOS technology scales down, process variation introduces significant uncertainty in power and performance to VLSI circuits and significantly affects their reliability. Although Static-Timing Analysis (STA) it is an excellent tool, but current trends in process scaling have imposed significant difficulties to STA. As one of the promising solutions, Statistical static timing analysis (SSTA) has become the frontier research topic in recent years in combating such variation effects. This paper will be focusing on two aspects of SSTA and its applications in VLSI designs: (1) Statistical timing modeling and analysis; and (2) Architectural implementations of the atomic operations (max and add). Experimental results have shown that our approach can provide 282 times speedup when compared to a conventional CPU implementation.

Reference this Research Paper (copy & paste below code):

Abu M. Baker, Yingtao Jiang (2018); Modeling and Architectural Simulations of the Statistical Static Timing Analysis of the Non-Gaussian Variation Sources for VLSI Circuits; Int J Sci Res Publ 3(1) (ISSN: 2250-3153). http://www.ijsrp.org/research-paper-1301.php?rp=P13614
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