International Journal of Scientific and Research Publications

IJSRP, Volume 2, Issue 11, November 2012 Edition [ISSN 2250-3153]

Design of Sample & Hold Circuit
      Amit Rajput, Seema Kanathe
Abstract: This paper describes the design of a high-speed CMOS Sample and Hold circuit in front of an analog to digital converter (ADC). Sample and hold (S/H) circuit employs linear source follower buffer at input and output. Synopsys cosmosSE software tool has been used for schematic design, H-spice for Simulation and Cscope for waveform performance. Complete S/H circuit has designed with tsmc035 (Taiwan semiconductor manufacturing corporation) technology, with 2.5V power supply. Power consumption of 5 mW for 8 MHz at 53 MS/s.

Reference this Research Paper (copy & paste below code):

Amit Rajput, Seema Kanathe (2018); Design of Sample & Hold Circuit; Int J Sci Res Publ 2(11) (ISSN: 2250-3153). http://www.ijsrp.org/research-paper-1112.php?rp=P11415
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