IJSRP, Volume 5, Issue 6, June 2015 Edition [ISSN 2250-3153]
SUVASINI SB , JAYARAM M V
In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling factors. Leakage power accounts for an increasingly larger portion of total power consumption in deep submicron technologies. Recently, in technology the power density has increased due to combination of higher clock speed, smaller process geometries and scaling factors, layout structure and greater functional integration.