International Journal of Scientific and Research Publications

IJSRP, Volume 5, Issue 6, June 2015 Edition [ISSN 2250-3153]


AREA AND POWER EFFICIENT CMOS ADDER DESIGN BY HYBRIDIZING PTL AND GDI TECHNIQUE
      SUVASINI SB , JAYARAM M V
Abstract: In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling factors. Leakage power accounts for an increasingly larger portion of total power consumption in deep submicron technologies. Recently, in technology the power density has increased due to combination of higher clock speed, smaller process geometries and scaling factors, layout structure and greater functional integration.

Reference this Research Paper (copy & paste below code):

SUVASINI SB , JAYARAM M V (2018); AREA AND POWER EFFICIENT CMOS ADDER DESIGN BY HYBRIDIZING PTL AND GDI TECHNIQUE; Int J Sci Res Publ 5(6) (ISSN: 2250-3153). http://www.ijsrp.org/research-paper-0615.php?rp=P424256
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