IJSRP, Volume 4, Issue 6, June 2014 Edition [ISSN 2250-3153]
Neelima.V, R. Ramesh Babu
In data processing processors, adder is a basic digital circuit. To perform any arithmetic operation, addition is the basic operation to perform. To compute fast arithmetic operations adder must be fastest. CSLA is the fastest adder when compare to RCA and CLA. From the structure of CSLA it is observed that there is a scope to reduce area further so that power can be lowered [3-4]. This paper proposes a new architecture of CSLA using reconfigurable adder structures (RAS) and is compared with regular SQRT CSLA, CSLA using BEC . The experimental analysis shows that the proposed CSLA using RAS is having advantages regarding area and power.