IJSRP, Volume 5, Issue 5, May 2015 Edition [ISSN 2250-3153]
Ravindra P Rajput, M. N Shanmukha Swamy
With the future 1 nm Hybrid CMOS technology, we proposed the Future Generation Ultra Supercomputing 256 × 256 Bits Multiplier for Signed-Unsigned Number. The Hybrid CMOS consists of the CMOS and Complimentary Pass Transistor Logic (CPTL). With the 1 nm future technology the various parameters predicted are the critical path delay of 0.1 ns (10 GHz), chip area of 136.23 𝛍m2 and the power dissipation of 1171.4 𝛍W.