International Journal of Scientific and Research Publications

IJSRP, Volume 3, Issue 4, April 2013 Edition [ISSN 2250-3153]


A Verilog Model of Universal Scalable Binary Sequence Detector
      P.V.Sasanka, Y.V.Ramana Rao, A.L.Siridhara
Abstract: This paper presents a Verilog based Universal Sequence Detector, which will be able to detect a binary sequence, from a sequence of inputs. The Sequence Detector looks for some specified sequence of inputs and outputs 1, whenever the desired sequence has found. The sequence detector is like a lock which unlocks (outputs 1), only when a combination appears. Coding of design is done in Verilog HDL and the design is tested and simulated in ModelSim Simulator and is implemented on Xilinx Virtex 4 XC4VFX12 FPGA device.

Reference this Research Paper (copy & paste below code):

P.V.Sasanka, Y.V.Ramana Rao, A.L.Siridhara (2018); A Verilog Model of Universal Scalable Binary Sequence Detector; Int J Sci Res Publ 3(4) (ISSN: 2250-3153). http://www.ijsrp.org/research-paper-0413.php?rp=P161078
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