Abstract: This paper presents a Verilog based Universal Sequence Detector, which will be able to detect a binary sequence, from a sequence of inputs. The Sequence Detector looks for some specified sequence of inputs and outputs 1, whenever the desired sequence has found. The sequence detector is like a lock which unlocks (outputs 1), only when a combination appears. Coding of design is done in Verilog HDL and the design is tested and simulated in ModelSim Simulator and is implemented on Xilinx Virtex 4 XC4VFX12 FPGA device.