International Journal of Scientific and Research Publications

IJSRP, Volume 5, Issue 3, March 2015 Edition [ISSN 2250-3153]


Low Power Techniques for High Speed FPGA
      P.A.Kamble, Prof M.B.Mali
Abstract: The motive of this work is to design on chip efficient low power techniques using VHDL coding. Serial links in network on chip provide many advantages in terms of crosstalk, skew, area cost, clock synchronization, and wiring difficulty when compared to multi-bit parallel data transmission. The proposed a novel coding technique reduces the number of transitions and hence reduces transmission energy on the serial wire. Also low power consumption is achieved by using the mux-tree based round robin scheduler. A scheduler (or arbiter) is needed when more than two input packets from different input ports are destined for the same output port at the same time.

Reference this Research Paper (copy & paste below code):

P.A.Kamble, Prof M.B.Mali (2018); Low Power Techniques for High Speed FPGA; Int J Sci Res Publ 5(3) (ISSN: 2250-3153). http://www.ijsrp.org/research-paper-0315.php?rp=P393816
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