IJSRP, Volume 3, Issue 3, March 2013 Edition [ISSN 2250-3153]
In many high speed Digital Signal Processing (DSP) and multimedia applications, the multiplier plays a very important role because it dominates the chip power consumption and operation speed. In DSP applications, in order to avoid infinite growth of multiplication bit width, it is necessary to reduce the number of multiplication products. Cutting off n-bit Less Significant Bit (LSB) output can construct a fixed width multiplier with n-bit input and n-bit output. However, truncating the LSB part leads to a large number of truncation errors. In order to avoid truncation error, error compensation circuit is designed with less truncation error and less hardware over head. A new error compensation circuit by using the dual group minor input correction vector to lower input correction vector compensation error is proposed. As compared with the conventional multiplier, the proposed fixed width modified booth multiplier performs not only with lower compensation error but also with lower hardware complexity, especially as multiplier input bits increase. In the proposed fixed width multiplier, the truncation error can be lowered compared with the direct truncated multiplier and the transistor count can be reduced compared with the full length multiplier.