International Journal of Scientific and Research Publications

IJSRP, Volume 3, Issue 3, March 2013 Edition [ISSN 2250-3153]


Design & Implementation of DWT – IDWT Algorithm for Image Compression by using FPGA
      Mahesh Goparaju, S Mohan
Abstract: Image compression is one of the major image processing techniques that is widely used in medical, automotive, consumer and military applications. Discrete wavelet transforms is the most popular transformation technique adopted for image compression. Complexity of DWT is always high due to large number of arithmetic operations. In this work a modified Distributive Arithmetic based DWT architecture is proposed and is implemented on FPGA. The modified approach consumes area of 6% on Spartan 3 FPGA and operates at 134 MHz. The modified DA-DWT architecture has a latency of 44 clock cycles and a throughput of 4 clock cycles. This design is twice faster than the reference design and is thus suitable for applications that require high speed image processing algorithms.

Reference this Research Paper (copy & paste below code):

Mahesh Goparaju, S Mohan (2018); Design & Implementation of DWT – IDWT Algorithm for Image Compression by using FPGA; Int J Sci Res Publ 3(3) (ISSN: 2250-3153). http://www.ijsrp.org/research-paper-0313.php?rp=P15883
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