International Journal of Scientific and Research Publications

IJSRP, Volume 3, Issue 3, March 2013 Edition [ISSN 2250-3153]

A Novel Low Power Optimization for On-Chip Interconnection
      B.Ganga Devi, S.Jayasudha
Abstract: This paper presents a low power design methodology for the Quasi Resonant Interconnection networks (QRN). This focuses mainly on reducing the power utilized at the receiver by replacing the existing delay element by a digitally controlled delay element. The analysis and design of the transmitter, receiver and the Interconnect and spiral inductor models are presented using 0.18µm CMOS technology. A very efficient reduction in power can be obtained by this method as about 0.12W is the power at the proposed receiver when compared to 50W in the existing receiver.

Reference this Research Paper (copy & paste below code):

B.Ganga Devi, S.Jayasudha (2018); A Novel Low Power Optimization for On-Chip Interconnection ; Int J Sci Res Publ 3(3) (ISSN: 2250-3153). http://www.ijsrp.org/research-paper-0313.php?rp=P15864
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