IJSRP, Volume 5, Issue 2, February 2015 Edition [ISSN 2250-3153]
Dr. A. Senthil Kumar, I.Manju, S.Sumathi, C.Preethi
In recent years the demand for low power devices has increased tremendously due to the migration of computer workstations to handheld devices that need real-time performance within the budget for physical size and energy dissipation. As a result of this there is a fast growth of battery operated portable applications such as PDAs, cell phones, laptops and other handheld devices. But also at the same time problems arising from continuous technology scaling have recently made power reduction an important design issue for the digital circuits and applications. Operating at low power causes SRAM read-stability and write- ability as major design constraints. The stability of read and write operations can be increased using Schmitt trigger based SRAM bit cells. In this paper the Schmitt trigger design is implemented in 8 transistor SRAM cell to increase read-stability and write-ability than the conventional 6T cell. The design is implemented in Tanner EDA tool and the results are observed.