International Journal of Scientific and Research Publications

IJSRP, Volume 5, Issue 2, February 2015 Edition [ISSN 2250-3153]


DESIGN OF HIGH SPEED AND LOW POWER 4T SRAM CELL
      P. Pavan Kumar, Dr. R Ramana Reddy, M.Lakshmi Prasanna Rani
Abstract: Portable devices demand for low power dissipation. To reduce power dissipation, the subsystem in a device needs to be designed to operate at low power and also consume low power. Significant progress has been made in low power design of dynamic RAM’s. Static RAM’s are also critical in most VLSI based system on chip applications. Basic SRAM bit cell consists of 6T. Few designs using 4T are also available in open literature. In this paper a highly reliable, low power and high speed SRAM design is proposed and comparisons were made with 6T and basic 4T SRAM designs.

Reference this Research Paper (copy & paste below code):

P. Pavan Kumar, Dr. R Ramana Reddy, M.Lakshmi Prasanna Rani (2018); DESIGN OF HIGH SPEED AND LOW POWER 4T SRAM CELL ; Int J Sci Res Publ 5(2) (ISSN: 2250-3153). http://www.ijsrp.org/research-paper-0215.php?rp=P383671
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