IJSRP, Volume 3, Issue 1, January 2013 Edition [ISSN 2250-3153]
Ch. Harish Kumar
The performance of the any processor will depend upon its power and delay. The power and delay should be less in order to get a effective processor. In processors the most commonly used architecture is multiplier. If the power and delay of the multiplier is reduced then the effective processor can be generated. The architectures for multipliers are mainly Array and Vedic multipliers. In Vedic multipliers there are two types of techniques for multiplications based on Urdhva Triyagbhyam and Nikhilam sutras. In this paper the comparison of these architectures is carried out to know the best architecture for multiplication w.r.t power and delay characteristics. The design of architectures are done in Verilog language and the tool used for simulation is Xilinx 10.1 ISE.