International Journal of Scientific and Research Publications

IJSRP, Volume 3, Issue 4, April 2013 Edition [ISSN 2250-3153]


FPGA Implementation of Hybrid Test Data Compression Method Using Scan Chain Compaction and Dictionary-based Scheme
      Sathiyapriya.R, Yuvasrri sindhu.M, ImmanuelRairosario.P
Abstract: The Goal in this paper is proposal of new test data compression method for reducing test data volume and test application time. The existing system in this paper is group the scan chain in the ascending order and it must be in odd number for group and the number of element in the groups. The proposed method consists of two steps: scan chain compaction (even or odd) and dictionary-based compression scheme. The scan chain compaction provides a minimum scan chain depth by using compaction of the compatible scan cells in the scan chain. The focus is to compacted scan chain is partitioned to the multiple internal scan chains it may be odd or even for using the fixed-length index dictionary-based compression scheme that provides the high compression ratio and the fast testing time. The proposed compression methods scan chain which is not arranged in ascending order and not in odd number. Hence it produces the output with four groups and it is implemented in FPGA using VHDL coding, where the existing system produces five groups, system delivers compressed patterns from the ATE to the chip and drives a large number of multiple internal scan chains using only a single ATE input and output. Experimental results for the test benches show that the test data volume and testing time for the proposed method are less than previous compression schemes.

Reference this Research Paper (copy & paste below code):

Sathiyapriya.R, Yuvasrri sindhu.M, ImmanuelRairosario.P (2018); FPGA Implementation of Hybrid Test Data Compression Method Using Scan Chain Compaction and Dictionary-based Scheme; Int J Sci Res Publ 3(4) (ISSN: 2250-3153). http://www.ijsrp.org/research-paper-0413.php?rp=P16998
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