International Journal of Scientific and Research Publications

IJSRP, Volume 3, Issue 4, April 2013 Edition [ISSN 2250-3153]


Design and Analysis of Low Power Pulse Triggered Flip-Flop
      S.P.Loga priya, P.Hemalatha
Abstract: Practically, clocking system like flip-flop (FF) consumes large portion of total chip power. In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. Pulse- triggered FF (P-FF) has been considered as a popular alternative to the conventional master –slave based FF in the applications of high speed. First, a simple two-transistor AND gate design is used to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. The maximum power saving against rival designs is up to 39.4%.Compared with the conventional transmission gate-based FF design; the average leakage power consumption is also reduced by a factor of 3.52

Reference this Research Paper (copy & paste below code):

S.P.Loga priya, P.Hemalatha (2018); Design and Analysis of Low Power Pulse Triggered Flip-Flop; Int J Sci Res Publ 3(4) (ISSN: 2250-3153). http://www.ijsrp.org/research-paper-0413.php?rp=P16976
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