Abstract: This project deals with a cyclic convolution of high speed parallel architecture based on Fermat number transform (FNT). Cyclic convolution architectures are implemented for operands in diminished-1 representation. The code conversion (CC) method is mandatory to convert normal binary numbers into their diminished-1 representation. In this paper we discuss about the FNT (Fermat Number Transform) and IFNT (Inverse Fermat Number Transform) operations which are performed by CCWA (Code Conversion without Addition) & BOWA (Butterfly Operation without Addition). The convolution which is the point wise multiplication is implemented by modulo 2n+1 partial product multipliers (MPPM) and these output partial products are the inputs to the IFNT and modulo 2n+1 carry propagation additions are avoided in the FNT and the IFNT except in their final stages The reduction of modulo 2n+1 carry propagation addition reduces the execution delay of the parallel architecture. The proposed one has better throughput performance and involves less hardware complexity than the existing cyclic convolution architecture.