International Journal of Scientific and Research Publications

IJSRP, Volume 3, Issue 3, March 2013 Edition [ISSN 2250-3153]


A Monotonic Digitally Programmable Delay Element for Low Power VLSI Applications
      S.Jayasudha, B.Ganga Devi
Abstract: Digitally programmable delay elements (DPDE) arerequired to be monotonic and low power. A lowpower digitally programmable delay element (DPDE) withmonotonic delay characteristics is proposed and a dynamiccurrent mirror together with a feedback technique enables acurrent-on-demand operation. The dynamic power is made proportional to the delay with a maximum of 25µW and static power is eliminated. DPDE is implemented with two new designs of CMOS digitally controlled oscillators(DCO).First design has been implemented withone driving strength controlled delay cell and with two NAND gates used as inverters. The second design with one delay cell and by two NOR gates is presented.

Reference this Research Paper (copy & paste below code):

S.Jayasudha, B.Ganga Devi (2018); A Monotonic Digitally Programmable Delay Element for Low Power VLSI Applications; Int J Sci Res Publ 3(3) (ISSN: 2250-3153). http://www.ijsrp.org/research-paper-0313.php?rp=P15865
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