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IJSRP, Volume 9, Issue 9, September 2019 Edition [ISSN 2250-3153]



      Ranganatha Gowda L R, Sujatha K

Abstract: Power is a key parameter in VLSI design. In this age of portable computers, battery life is very important. Power convergence is an important factor from a designer perspective. All applications demand chip level power reduction. Power and timing convergence goes hand in hand. One cannot be compromised for other, here comes the challenge for a designer. This paper focuses on understanding of various power sources and solutions for power reduction in a physical design. Enhanced quality rules are proposed for the high quality performance of the design. The enhanced power reduction techniques for both Data path power reduction and Clock path power reduction are mainly

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Ranganatha Gowda L R, Sujatha K (2019); Power Optimization Techniques in VLSI Backend Design; International Journal of Scientific and Research Publications (IJSRP) 9(9) (ISSN: 2250-3153), DOI: http://dx.doi.org/10.29322/IJSRP.9.09.2019.p9334

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