Abstract: The Visibility Representations [1] of a graph has been promoted for research extensively because of their significance in algorithmic graph theory as well as in VLSI layout, algorithm animation, visual languages and CASE tools etc. [2][3]. Rectangle Visibility Graph (RVG) used in VLSI chip design represents the node of a graph as a rectangle in a plane. Unit Rectangle Visibility Graph (URVG) means a presentation where each node is represented as unit rectangle in the plane. So, Unit Rectangle Visibility graph is applied for fixed dimensions of gates and various circuit components in computer chip applications. In this research, binary tree and ternary tree have been characterized as URV representations which will not only enhance URVR (Unit Rectangle Visibility Representation) but also expected to reduce both cost and labor in the field of various graph applications. To achieve this, two novel algorithms for URVR of these trees have been proposed.