Speedy Convolution Using Reversible Vedic Multiplier

Anuja George, Sreethu Raj

Abstract


This paper presents a novel method for convolution of two finite length sequences using hardware description
language(VHDL). Convolution is widely used in digital signal processing. The proposed design replaces conventional multiplier with
reversible Vedic multiplier. The proposed design consumes only less area and have higher speed than existing method. Vedic
mathematics is world renowned for its quicker mental calculation approach. Urdhva Tiryakbhyam Vedic multiplier is efficient in
terms of both power and speed. The comparison of existing method with conventional is done using XILINX software.

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