Abstract: Synchronous stream ciphers are lightweight symmetric-key cryptosystems which encrypt a plain-text or decrypt a cipher-text. This project includes two new hardware designs of the Welch–Gong (WG)−128 cipher, one for the multiple output WG (MOWG) version, and the other for the single output version WG based on type−II optimal normal basis representation. The proposed MOWG design uses signal reuse techniques to reduce hardware cost in the MOWG transformation, whereas it increases the speed by eliminating the inverters from the critical path. This is accomplished through reconstructing the key and initial vector loading algorithm and the feedback polynomial of the linear feedback shift register. The proposed WG design uses properties of the trace function to optimize the hardware cost in the WG transformation. The security of WG and MOWG ciphers are increased by providing one way encryption to the initial vector using cryptographic hash functions. The proposed designs have less area and power consumptions than the existing implementations of the WG cipher. The software used for simulation is Xilinx ISE and the programming language used is VHDL. Hardware implementation of the project is done using Spartan-3E FPGA.