Abstract: Pulse-triggered flip-flops are mainly used to improve speed of operation (pipeline speed), though flip-flop robustness and system timing closure are challenging in a wide range of supply voltages. Usually pulse-triggered flip-flops have specific structures and transistor sizes to optimize the system performance. The transistor size, topology, and threshold voltage of the flip-flop make the timing characteristics sensitive to the supply voltage. The transparent windows generated and required in a pulse-triggered flip-flop may have mismatch under different supply voltages (scaling), which is likely to result in system timing and functional failures. in single edge adaptive pulse trigger flip-flops the latching speed is less, no of transistors are more and power dissipation also high so to overcome these limitations dual edge adaptive pulse triggered flip flop is proposed. Proposed structure improves the robustness of adaptive pulse-triggered flip-flops and promises this high-speed clocked element for wide range of supply voltages so data latching speed is increase, numbers of transistors were reduced and power dissipation also reduced. Transistor driving-strength mismatches are considered and overcome by Dual edge adaptive pulse trigger flip flop implemented in 130nm technology.