Abstract: This paper presents an efficient VLSI architecture for a 4x4 64-QAM multiple-input–multiple-output (MIMO) detector. The augmentation is done by on demand expansion of intermediate nodes of the tree rather than exhaustively, along with pipelined distributed sorters. The proposed architecture has a stable critical path independent of constellation size, scalable to higher number of antennas with efficient distributed sorters. Further, modification will be carried out with the faster multiplication unit to make it scalable to higher number of antennas.