Abstract: Viterbi Decoder (VD) employed in digital wireless communication plays a dominant role in the overall power consumption of trellis coded modulation (TCM) decoder. Power reduction in VD could be achieved by reducing the number of states. A pre-computation architecture with T-algorithm was implemented for this purpose, and when we compare this result with full Trellis VD, this approach significantly reduces power consumption without degrading decoding speed much . Low power design of VD for TCM systems with reliable delay is presented in this paper. This work focuses on the realization of convolutional encoder and adaptive Viterbi decoder (AVD) with a constraint length (K) of 9 and a code rate (k/n) of ½ using field programmable gate array (FPGA) technology. The performance of the implemented AVD is analyzed by using ISE 10.1 and Modelsim simulations.