Abstract: Mitigation of transient hardware faults in FPGA requires measures, either in pure software that results in runtime and memory overhead or specific hardware design approach like full or partial duplication of functionalities resulting in an area overhead. In this paper, duplication of CPU using standard soft-core processor and implementation in FPGA for fault-tolerant applications in nuclear power plant is proposed. The combination of FPGA technology and soft processor cores has the potential to allow the integration of system design into a single FPGA device. They can be also combined in one chip, leading to less power consumption, simpler board layout and fewer problems with signal integrity and EMI (electromagnetic interference).This combination can provide previously unavailable design options. Paper work aims towards the realization of a dual core processor on FPGA