Abstract: In this paper we propose an efficient pipelined architecture for low power,high throughput and low area adaptive FIR filter based on distributed airthemetic. The throughput rate is significantly increased by parallel look-up table(LUT) update. Reduction in power consumption is achieved by using a fast bit clock for carry save accumulation. We have shown that sampling period could be sequentially reduced by using carry save accumulation for DA based inner product. It involves half the number of register compared to the existing DA based design to store of input samples. The system is implemented in FPGA that enables rapid prototyping of digital cirtcuits.